| Vector | Constant | Note |
| #SS 12 | c_ss0000 | A memory address exceeded the stack segment limit or was non-canonical. |
| #GP 13 | c_gp0001 | A memory address exceeded a data segment limit or was noncanonical. |
| #GP 13 | c_gp0002 | The destination operand was in a non-writable segment. |
| #GP 13 | c_gp0003 | A null data segment was used to reference memory. |
| #PF 14 | c_pf0004 | A page fault resulted from the execution of the instruction. |
| #AC 17 | c_ac0005 | An unaligned memory reference was performed while alignment checking was enabled. |
| #NP 11 | c_np0006 | The DS, ES, FS, or GS register was loaded with a non-null segment selector and the segment was marked not present. |
| #SS 12 | c_ss0007 | The SS register was loaded with a non-null segment selector and the segment was marked not present. |
| #GP 13 | c_gp0008 | A segment register was loaded and the segment descriptor exceeded the descriptor table limit. |
| #GP 13 | c_gp0009 | A segment register was loaded and the segment selectors TI bit was set, but the LDT selector was a null selector. |
| #GP 13 | c_gp0010 | The SS register was loaded with a null segment selector in non-64-bit mode or while CPL = 3. |
| #GP 13 | c_gp0011 | The SS register was loaded and the segment selector RPL and the segment descriptor DPL were not equal to the CPL. |
| #GP 13 | c_gp0012 | The SS register was loaded and the segment pointed to was not a writable data segment. |
| #GP 13 | c_gp0013 | The DS, ES, FS, or GS register was loaded and the segment pointed to was a data or non-conforming code segment, but the RPL or the CPL was greater than the DPL. |
| #GP 13 | c_gp0014 | The DS, ES, FS, or GS register was loaded and the segment pointed to was not a data segment or readable code segment. |
| #SS 12 | c_ss0015 | A memory address exceeded the stack segment limit. |
| #BR 5 | c_br0016 | The bound range was exceeded. |
| #GP 13 | c_gp0017 | A memory address exceeded a data segment limit. |
| #SS 12 | c_ss0018 | A memory address was non-canonical. |
| #GP 13 | c_gp0019 | A memory address was non-canonical. |
| #UD 6 | c_ud0020 | This instruction is only recognized in protected legacy and compatibility mode. |
| #GP 13 | c_gp0021 | A null segment selector was used to reference memory. |
| #GP 13 | c_gp0022 | One or more I/O permission bits were set in the TSS for the accessed port. |
| #GP 13 | c_gp0023 | The CPL was greater than the IOPL and one or more I/O permission bits were set in the TSS for the accessed port. |
| #GP 13 | c_gp0024 | The target offset exceeded the code segment limit or was noncanonical. |
| #SS 12 | c_ss0025 | The SS register was loaded with a non-null segment selector, and the segment was marked not present. |
| #GP 13 | c_gp0026 | A segment register was loaded, but the segment descriptor exceeded the descriptor table limit. |
| #UD 6 | c_ud0027 | An illegal control register was referenced (CR1, CR5CR7, CR9CR15). |
| #UD 6 | c_ud0028 | The use of the LOCK prefix to read CR8 is not supported, as indicated by ECX bit 4 as returned by CPUID function 8000_0001h. |
| #GP 13 | c_gp0029 | CPL was not 0. |
| #GP 13 | c_gp0030 | An attempt was made to set CR0.PG = 1 and CR0.PE = 0. |
| #GP 13 | c_gp0031 | An attempt was made to set CR0.CD = 0 and CR0.NW = 1. |
| #GP 13 | c_gp0032 | Reserved bits were set in the page-directory pointers table (used in the legacy extended physical addressing mode) and the instruction modified CR0, CR3, or CR4. |
| #GP 13 | c_gp0033 | An attempt was made to write 1 to any reserved bit in CR0, CR3, CR4 or CR8. |
| #GP 13 | c_gp0034 | An attempt was made to set CR0.PG while long mode was enabled (EFER.LME = 1), but paging address extensions were disabled (CR4.PAE = 0). |
| #GP 13 | c_gp0035 | An attempt was made to clear CR4.PAE while long mode was active (EFER.LMA = 1). |
| #DB 1 | c_db0036 | A debug register was referenced while the general detect (GD) bit in DR7 was set. |
| #UD 6 | c_ud0037 | DR4 or DR5 was referenced while the debug extensions (DE) bit in CR4 was set. |
| #UD 6 | c_ud0038 | An illegal debug register (DR8DR15) was referenced. |
| #GP 13 | c_gp0039 | A 1 was written to any of the upper 32 bits of DR6 or DR7 in 64-bit mode. |
| #TS 10 | c_ts0040 | As part of a stack switch, the target stack segment selector or rSP in the TSS was beyond the TSS limit. |
| #TS 10 | c_ts0041 | As part of a stack switch, the target stack segment selector in the TSS was a null selector. |
| #TS 10 | c_ts0042 | As part of a stack switch, the target stack selectors TI bit was set, but LDT selector was a null selector. |
| #TS 10 | c_ts0043 | As part of a stack switch, the target stack segment selector in the TSS was beyond the limit of the GDT or LDT descriptor table. |
| #TS 10 | c_ts0044 | As part of a stack switch, the target stack segment selector in the TSS contained a RPL that was not equal to its DPL. |
| #TS 10 | c_ts0045 | As part of a stack switch, the target stack segment selector in the TSS contained a DPL that was not equal to the CPL of the code segment selector. |
| #TS 10 | c_ts0046 | As part of a stack switch, the target stack segment selector in the TSS was not a writable segment. |
| #NP 11 | c_np0047 | The accessed code segment, call gate, task gate, or TSS was not present. |
| #SS 12 | c_ss0048 | After a stack switch, a memory address exceeded the stack segment limit or was non-canonical. |
| #SS 12 | c_ss0049 | As part of a stack switch, the SS register was loaded with a non-null segment selector and the segment was marked not present. |
| #GP 13 | c_gp0050 | The target code segment selector was a null selector. |
| #GP 13 | c_gp0051 | A code, call gate, task gate, or TSS descriptor exceeded the descriptor table limit. |
| #GP 13 | c_gp0052 | A segment selectors TI bit was set but the LDT selector was a null selector. |
| #GP 13 | c_gp0053 | The segment descriptor specified by the instruction was not a code segment, task gate, call gate or available TSS in legacy mode, or not a 64-bit code segment or a 64-bit call gate in long mode. |
| #GP 13 | c_gp0054 | The RPL of the non-conforming code segment selector specified by the instruction was greater than the CPL, or its DPL was not equal to the CPL. |
| #GP 13 | c_gp0055 | The DPL of the conforming code segment descriptor specified by the instruction was greater than the CPL. |
| #GP 13 | c_gp0056 | The DPL of the callgate, taskgate, or TSS descriptor specified by the instruction was less than the CPL, or less than its own RPL. |
| #GP 13 | c_gp0057 | The segment selector specified by the call gate or task gate was a null selector. |
| #GP 13 | c_gp0058 | The segment descriptor specified by the call gate was not a code segment in legacy mode, or not a 64-bit code segment in long mode. |
| #GP 13 | c_gp0059 | The DPL of the segment descriptor specified by the call gate was greater than the CPL. |
| #GP 13 | c_gp0060 | The 64-bit call gates extended attribute bits were not zero. |
| #GP 13 | c_gp0061 | The TSS descriptor was found in the LDT. |
| #NM 7 | c_nm0062 | The monitor coprocessor bit (MP) and the task switch bit (TS) of the control register (CR0) were both set to 1. |
| #MF 16 | c_mf0063 | An unmasked x87 floating-point exception was pending. |
| #GP 13 | c_gp0064 | The I/O privilege level was less than 3 and either VME was not enabled or the operand size was not 16-bit. |
| #GP 13 | c_gp0065 | The I/O privilege level was less than 3 and one of the following
conditions was true:
CR4.VME was 0. The effective operand size was 32-bit. Both the original EFLAGS.VIP and the new EFLAGS.IF bits were set. The new EFLAGS.TF bit was set. |
| #UD 6 | c_ud0066 | This instruction is not supported in 64-bit mode, as indicated by ECX bit 0 returned by CPUID function 8000_0001h. |
| #UD 6 | c_ud0067 | The SSE2 instructions are not supported, as indicated by EDX bit 26 of CPUID function 0000_0001h. |
| #UD 6 | c_ud0068 | The emulate bit (EM) of CR0 was set to 1. |
| #UD 6 | c_ud0069 | The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. |
| #NM 7 | c_nm0070 | The task-switch bit (TS) of CR0 was set to 1. |
| #UD 6 | c_ud0071 | There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT was cleared to 0. |
| #XF 19 | c_xf0072 | A source operand was an SNaN value. |
| #XF 19 | c_xf0073 | A source operand was a QNaN value, and the comparison does not allow QNaN values. |
| #XF 19 | c_xf0074 | A source operand was a denormal value. |
| #GP 13 | c_gp0075 | A memory address exceeded the ES segment limit or was non-canonical. |
| #GP 13 | c_gp0076 | The ES segment was a non-writable segment. |
| #GP 13 | c_gp0077 | A null ES segment was used to reference memory. |
| #UD 6 | c_ud0078 | The PREFETCH/W instructions are not supported, as indicated when the
following bits are all clear:
PREFETCH/PREFETCHW are not supported, as indicated by ECX bit 8 of CPUID function 8000_0001h Long Mode is not supported, as indicated by EDX bit 29 of CPUID function 8000_0001h The 3DNow! instructions are not supported, as indicated by EDX bit 31 of CPUID function 8000_0001h. |
| #UD 6 | c_ud0079 | IF CR4.SMXE = 0. |
| #UD 6 | c_ud0080 | If GETSEC[eax] is not reported as supported by GETSEC[CAPABILITIES]. |
| #GP 13 | c_gp0081 | GETSEC[eax] is not recognized in real-address mode. |
| #GP 13 | c_gp0082 | GETSEC[eax] is not recognized in virtual-8086 mode. |
| #GP 13 | c_gp0083 | IF AC code module does not reside in physical address below 2^32 -1. |
| #GP 13 | c_gp0084 | If the processor is not currently in authenticated code execution mode. |
| #GP 13 | c_gp0085 | If CR0.CD = 1 or CR0.NW = 1 or CR0.NE = 0 or CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1. |
| #GP 13 | c_gp0086 | If a Intel TXT-capable chipset is not present. |
| #GP 13 | c_gp0087 | If in VMX root operation. |
| #GP 13 | c_gp0088 | If the initiating processor is not designated as the bootstrap processor via the MSR bit IA32_APIC_BASE.BSP. |
| #GP 13 | c_gp0089 | If the processor is already in authenticated code execution mode. |
| #GP 13 | c_gp0090 | If the processor is in SMM. |
| #GP 13 | c_gp0091 | If a valid uncorrectable machine check error is logged in IA32_MC[I]_STATUS. |
| #GP 13 | c_gp0092 | If the authenticated code base is not on a 4096 byte boundary. |
| #GP 13 | c_gp0093 | If the authenticated code size > processor internal authenticated code area capacity. |
| #GP 13 | c_gp0094 | If the authenticated code size is not modulo 64. |
| #GP 13 | c_gp0095 | If other enabled logical processor(s) of the same package CR0.CD = 1. |
| #GP 13 | c_gp0096 | If other enabled logical processor(s) of the same package are not in the wait-for-SIPI or SENTER sleep state. |
| #GP 13 | c_gp0097 | If the target address in RBX is not in a canonical form. |
| #GP 13 | c_gp0098 | If CR0.PE = 0 or CPL>0 or EFLAGS.VM =1. |
| #GP 13 | c_gp0099 | If any reserved bit position is set in the EDX parameter register. |
| #GP 13 | c_gp0100 | If an Intel TXT-capable chipset interface to TPM is not detected as present. |
| #GP 13 | c_gp0101 | If a protected partition is already active or the processor is already in authenticated code mode. |
| #GP 13 | c_gp0102 | If the authenticated code size > processor's authenticated code execution area storage capacity. |
| #GP 13 | c_gp0103 | If the SMM monitor is not configured. |
| #NP 11 | c_np0104 | The return code segment was marked not present. |
| #SS 12 | c_ss0105 | The return stack segment was marked not present. |
| #GP 13 | c_gp0106 | The return code selector was a null selector. |
| #GP 13 | c_gp0107 | The return stack selector was a null selector and the return mode was non-64-bit mode or CPL was 3. |
| #GP 13 | c_gp0108 | The return code or stack descriptor exceeded the descriptor table limit. |
| #GP 13 | c_gp0109 | The return code or stack selectors TI bit was set but the LDT selector was a null selector. |
| #GP 13 | c_gp0110 | The segment descriptor for the return code was not a code segment. |
| #GP 13 | c_gp0111 | The RPL of the return code segment selector was less than the CPL. |
| #GP 13 | c_gp0112 | The return code segment was non-conforming and the segment selectors DPL was not equal to the RPL of the code segments segment selector. |
| #GP 13 | c_gp0113 | The return code segment was conforming and the segment selectors DPL was greater than the RPL of the code segments segment selector. |
| #GP 13 | c_gp0114 | The segment descriptor for the return stack was not a writable data segment. |
| #GP 13 | c_gp0115 | The stack segment descriptor DPL was not equal to the RPL of the return code segment selector. |
| #GP 13 | c_gp0116 | The stack segment selector RPL was not equal to the RPL of the return code segment selector. |
| #NP 11 | c_np0117 | The accessed code segment, interrupt gate, trap gate, task gate, or TSS was not present. |
| #GP 13 | c_gp0118 | The IOPL was less than 3 and CR4.VME was 0. |
| #GP 13 | c_gp0119 | IOPL was less than 3, CR4.VME was 1, and the corresponding bit in the VME interrupt redirection bitmap was 1. |
| #GP 13 | c_gp0120 | The interrupt vector was beyond the limit of IDT. |
| #GP 13 | c_gp0121 | The descriptor in the IDT was not an interrupt, trap, or task gate in legacy mode or not a 64-bit interrupt or trap gate in long mode. |
| #GP 13 | c_gp0122 | The DPL of the interrupt, trap, or task gate descriptor was less than the CPL. |
| #GP 13 | c_gp0123 | The segment selector specified by the interrupt or trap gate had its TI bit set, but the LDT selector was a null selector. |
| #GP 13 | c_gp0124 | The segment descriptor specified by the interrupt or trap gate exceeded the descriptor table limit or was a null selector. |
| #GP 13 | c_gp0125 | The segment descriptor specified by the interrupt or trap gate was not a code segment in legacy mode, or not a 64-bit code segment in long mode. |
| #GP 13 | c_gp0126 | The DPL of the segment specified by the interrupt or trap gate was greater than the CPL. |
| #GP 13 | c_gp0127 | The DPL of the segment specified by the interrupt or trap gate pointed was not 0 or it was a conforming segment. |
| #OF 4 | c_of0128 | The INTO instruction was executed with OF set to 1. |
| #BP 3 | c_bp0129 | INT 3 instruction was executed. |
| #TS 10 | c_ts0130 | As part of a stack switch, the target stack segment selectors TI bit was set, but the LDT selector was a null selector. |
| #SS 12 | c_ss0131 | After a stack switch, a memory address exceeded the stack segment limit or was non-canonical and a stack switch occurred. |
| #DB 1 | c_db0132 | INT 1 instruction was executed. |
| #GP 13 | c_gp0133 | IRETx was executed in long mode while EFLAGS.NT=1. |
| #DE 0 | c_de0134 | 8-bit immediate value was 0. |
| #GP 13 | c_gp0135 | The CPL was greater than the IOPL and virtual mode extensions are not enabled (CR4.VME = 0). |
| #GP 13 | c_gp0136 | The CPL was greater than the IOPL and either the CPL was not 3 or protected mode virtual interrupts were not enabled (CR4.PVI = 0). |
| #GP 13 | c_gp0137 | This instruction would set RFLAGS.VIF to 1 and RFLAGS.VIP was already 1. |
| #DE 0 | c_de0138 | The divisor operand was 0. |
| #DE 0 | c_de0139 | The quotient was too large for the designated register. |
| #UD 6 | c_ud0140 | This instruction is only recognized in protected mode. |
| #NP 11 | c_np0141 | The LDT descriptor was marked not present. |
| #GP 13 | c_gp0142 | The source selector did not point into the GDT. |
| #GP 13 | c_gp0143 | The descriptor was beyond the GDT limit. |
| #GP 13 | c_gp0144 | The descriptor was not an LDT descriptor. |
| #GP 13 | c_gp0145 | The descriptor's extended attribute bits were not zero in 64- bit mode. |
| #GP 13 | c_gp0146 | The new LDT base address was non-canonical. |
| #NP 11 | c_np0147 | The TSS descriptor was marked not present. |
| #GP 13 | c_gp0148 | The new TSS selector was a null selector. |
| #GP 13 | c_gp0149 | The descriptor was not an available TSS descriptor. |
| #GP 13 | c_gp0150 | The new TSS base address was non-canonical. |
| #GP 13 | c_gp0151 | The new GDT base address was non-canonical. |
| #UD 6 | c_ud0152 | The RDTSCP instruction is not supported, as indicated by EDX bit 27 returned by CPUID function 8000_0001h. |
| #GP 13 | c_gp0153 | CPL was not 0 and CR4.TSD = 1. |
| #UD 6 | c_ud0154 | The SVM instructions are not supported as indicated by ECX bit 2 as returned by CPUID function 8000_0001h. |
| #UD 6 | c_ud0155 | Secure Virtual Machine was not enabled (EFER.SVME=0). |
| #UD 6 | c_ud0156 | The instruction is only recognized in protected mode. |
| #GP 13 | c_gp0157 | rAX referenced a physical address above the maximum supported physical address. |
| #GP 13 | c_gp0158 | The address in rAX was not aligned on a 4Kbyte boundary. |
| #UD 6 | c_ud0159 | If executed outside VMX non-root operation. |
| #UD 6 | c_ud0160 | A logical processor cannot be in real-address mode while in VMX operation and this instruction is not recognized outside VMX operation. |
| #GP 13 | c_gp0161 | If the current privilege level is not 0 and the logical processor is in VMX root operation. |
| #GP 13 | c_gp0162 | VMMCALL was not intercepted. |
| #UD 6 | c_ud0163 | Secure Virtual Machine was not enabled (EFER.SVME=0) and both of the
following conditions were true:
SVM-Lock is not available, as indicated by EDX bit 2 returned by CPUID function 8000_000Ah. DEV is not available, as indicated by ECX bit 12 returned by CPUID function 8000_0001h. |
| #UD 6 | c_ud0164 | The MONITOR/MWAIT instructions are not supported, as indicated by ECX bit 3 (Monitor) as returned by CPUID function 0000_0001h. |
| #UD 6 | c_ud0165 | CPL was not zero and MSR C001_0015[MonMwaitUserEn] = 0. |
| #GP 13 | c_gp0166 | ECX was non-zero. |
| #GP 13 | c_gp0167 | Unsupported extension bits were set in ECX |
| #UD 6 | c_ud0168 | The MFENCE instruction is not supported as indicated by bit 26 of CPUID function 0000_0001h. |
| #UD 6 | c_ud0169 | The LFENCE instruction is not supported as indicated by EDX bit 26 of CPUID function 0000_0001h. |
| #UD 6 | c_ud0170 | The SSE instructions are not supported, as indicated by EDX bit 25 of CPUID function 0000_0001h; and the AMD extensions to MMX are not supported, as indicated by EDX bit 22 of CPUID function 8000_0001h. |
| #UD 6 | c_ud0171 | The CMPXCHG8B instruction is not supported, as indicated by EDX bit 8 of CPUID function 0000_0001h or function 8000_0001h. |
| #UD 6 | c_ud0172 | The CMPXCHG16B instruction is not supported, as indicated by ECX bit 13 of CPUID function 0000_0001h. |
| #GP 13 | c_gp0173 | The memory operand for CMPXCHG16B was not aligned on a 16-byte boundary. |
| #GP 13 | c_gp0174 | The memory operand was not aligned on a 16-byte boundary while MXCSR.MM was cleared to 0. |
| #AC 17 | c_ac0175 | An unaligned memory reference was performed while alignment checking was enabled with MXCSR.MM set to 1. |
| #UD 6 | c_ud0176 | The MMX instructions are not supported, as indicated by EDX bit 23 in CPUID function 0000_0001h or function 8000_0001h. |
| #UD 6 | c_ud0177 | The FXSAVE/FXRSTOR instructions are not supported, as indicated by EDX bit 24 of CPUID function 0000_0001h or function 8000_0001h. |
| #GP 13 | c_gp0178 | The memory operand was not aligned on a 16-byte boundary. |
| #UD 6 | c_ud0179 | The SSE instructions are not supported, as indicated by EDX bit 25 of CPUID function 0000_0001h. |
| #GP 13 | c_gp0180 | Ones were written to the reserved bits in MXCSR. |
| #UD 6 | c_ud0181 | The CLFLUSH instruction is not supported, as indicated by EDX bit 19 of CPUID function 0000_0001h. |
| #UD 6 | c_ud0182 | The SSE4A instructions are not supported, as indicated by ECX bit 6 (SSE4A) of CPUID function 8000_0001h. |
| #GP 13 | c_gp0183 | The extended attribute bits of a system descriptor was not zero in 64-bit mode. |
| #UD 6 | c_ud0184 | The SYSCALL and SYSRET instructions are not supported, as indicated by EDX bit 11 returned by CPUID function 8000_0001h. |
| #UD 6 | c_ud0185 | The system call extension bit (SCE) of the extended feature enable register (EFER) is set to 0. (The EFER register is MSR C000_0080h.) |
| #UD 6 | c_ud0186 | This instruction is not recognized. |
| #UD 6 | c_ud0187 | The AMD 3DNow! instructions are not supported, as indicated by EDX bit 31 in CPUID function 8000_0001h. |
| #UD 6 | c_ud0188 | The SSE instructions are not supported, as indicated by EDX bit 25 of CPUID function 0000_0001h. |
| #UD 6 | c_ud0189 | The SSE3 instructions are not supported, as indicated by ECX bit 0 of CPUID function 0000_0001h. |
| #XF 19 | c_xf0190 | A result could not be represented exactly in the destination format. |
| #XF 19 | c_xf0191 | A source operand was an SNaN value, a QNaN value, or infinity. |
| #XF 19 | c_xf0192 | A source operand was too large to fit in the destination format. |
| #UD 6 | c_ud0193 | The WRMSR instruction is not supported, as indicated by EDX bit 5 returned by CPUID function 1 or 8000_0001h. |
| #GP 13 | c_gp0194 | The value in ECX specifies a reserved or unimplemented MSR address. |
| #GP 13 | c_gp0195 | Writing 1 to any bit that must be zero (MBZ) in the MSR. |
| #GP 13 | c_gp0196 | Writing a non-canonical value to a MSR that can only be written with canonical values. |
| #UD 6 | c_ud0197 | The RDTSC instruction is not supported, as indicated by EDX bit 4 returned by CPUID function 0000_0001h or function 8000_0001h. |
| #UD 6 | c_ud0198 | The RDMSR instruction is not supported, as indicated by EDX bit 5 returned by CPUID function 0000_0001h or function 8000_0001h. |
| #GP 13 | c_gp0199 | The value in ECX specified an unimplemented performance counter number. |
| #GP 13 | c_gp0200 | CPL was not 0 and CR4.PCE = 0. |
| #UD 6 | c_ud0201 | The SYSENTER and SYSEXIT instructions are not supported, as indicated by EDX bit 11 returned by CPUID function 0000_0001h. |
| #GP 13 | c_gp0202 | This instruction is not recognized in real mode. |
| #GP 13 | c_gp0203 | MSR_SYSENTER_CS was a null selector. |
| #UD 6 | c_ud0204 | The CMOVcc instruction is not supported, as indicated by EDX bit 15 of CPUID function 0000_0001h or function 8000_0001h. |
| #XF 19 | c_xf0205 | A source operand was negative (not including 0). |
| #XF 19 | c_xf0206 | +infinity was added to infinity. |
| #XF 19 | c_xf0207 | A rounded result was too large to fit into the format of the destination operand. |
| #XF 19 | c_xf0208 | A rounded result was too small to fit into the format of the destination operand. |
| #XF 19 | c_xf0209 | Zero was multiplied by infinity. |
| #XF 19 | c_xf0210 | +infinity was subtracted from +infinity. |
| #XF 19 | c_xf0211 | infinity was subtracted from infinity. |
| #XF 19 | c_xf0212 | A source operand was an SNaN or QNaN value. |
| #XF 19 | c_xf0213 | Zero was divided by zero. |
| #XF 19 | c_xf0214 | infinity was divided by infinity. |
| #XF 19 | c_xf0215 | A non-zero number was divided by zero. |
| #XF 19 | c_xf0216 | The instruction used XMM registers while CR4.OSFXSR=0. |
| #XF 19 | c_xf0217 | An x87 floating-point exception was pending and the instruction referenced an MMX register. |
| #UD 6 | c_ud0218 | The processor was not in System Management Mode (SMM). |
| #UD 6 | c_ud0219 | The POPCNT instruction is not supported, as indicated by ECX bit 23 as returned by CPUID function 0000_0001h. |
| #UD 6 | c_ud0220 | The AMD 3DNow! instructions are not supported, as indicated by EDX bit 31 in CPUID function 8000_0001h. |
| #MF 16 | c_mf0221 | A source operand was an SNaN value or an unsupported format. |
| #MF 16 | c_mf0222 | +infinity was added to infinity. |
| #MF 16 | c_mf0223 | An x87 stack underflow occurred. |
| #MF 16 | c_mf0224 | A source operand was a denormal value. |
| #MF 16 | c_mf0225 | A rounded result was too large to fit into the format of the destination operand. |
| #MF 16 | c_mf0226 | A rounded result was too small to fit into the format of the destination operand. |
| #MF 16 | c_mf0227 | A result could not be represented exactly in the destination format. |
| #MF 16 | c_mf0228 | A source operand was an SNaN value, a QNaN value, or an unsupported format. |
| #MF 16 | c_mf0229 | +infinity was subtracted from +infinity. |
| #MF 16 | c_mf0230 | infinity was subtracted from infinity. |
| #MF 16 | c_mf0231 | infinity was divided by infinity. |
| #MF 16 | c_mf0232 | zero was divided by zero. |
| #MF 16 | c_mf0233 | A non-zero value was divided by zero. |
| #MF 16 | c_mf0234 | A source operand was a denormal value. This exception does not occur if the source operand was in doubleextended- precision format. |
| #MF 16 | c_mf0235 | A source operand was an SNaN value. |
| #MF 16 | c_mf0236 | A source operand was in an unsupported format. |
| #MF 16 | c_mf0237 | An x87 stack overflow occurred. |
| #MF 16 | c_mf0238 | ST(0) was infinity. |
| #MF 16 | c_mf0239 | ST(1) was zero. |
| #MF 16 | c_mf0240 | The source operand in ST(0) was a negative finite value (not -zero). |
| #MF 16 | c_mf0241 | The source operand in ST(0) was +1 and the source operand in ST(1) was infinity. |
| #MF 16 | c_mf0242 | The source operand in ST(0) was -infinity. |
| #MF 16 | c_mf0243 | The source operand in ST(0) was zero or infinity and the source operand in ST(1) was zero. |
| #MF 16 | c_mf0244 | The source operand in ST(0) was zero and the source operand in ST(1) was a finite value. |
| #MF 16 | c_mf0245 | The source operand in ST(0) was 0 and the source operand in ST(1) was infinity. |
| #MF 16 | c_mf0246 | A source operand was infinity |
| #MF 16 | c_mf0247 | A source operand was a negative value (not including - zero). |
| #MF 16 | c_mf0248 | A source operand was infinity. |
| #MF 16 | c_mf0249 | A source operand was a SNaN value, a QNaN value, or an unsupported format. |
| #MF 16 | c_mf0250 | The source operand was zero. |
| #MF 16 | c_mf0251 | The source operand was not an integral value. |
| #UD 6 | c_ud0252 | The Conditional Move instructions are not supported, as indicated by EDX bit 0 and EDX bit 15 in CPUID function 0000_0001h or function 8000_0001h. |
| #MF 16 | c_mf0253 | The source operand was too large for the destination format. |
| #MF 16 | c_mf0254 | A source operand was an SNaN value, a QNaN value, infinity or an unsupported format. |
| #MF 16 | c_mf0255 | A source operand was too large to fit in the destination format. |
| #MF 16 | c_mf0256 | A result could not be represented exactly in the destination format. |
| #UD 6 | c_ud0257 | This instruction is not recognized in virtual-8086 mode. |
| #UD 6 | c_ud0258 | This instruction is not recognized in compatibility mode. |
| #GP 13 | c_gp0259 | If the current privilege level is not 0. If a memory destination operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains an unusable segment. If the destination operand is located in a read-only data segment or any code segment. |
| #PF 14 | c_pf0260 | If a page fault occurs in accessing a memory destination operand. |
| #SS 12 | c_ss0261 | If a memory destination operand effective address is outside the SS segment limit. If the SS register contains an unusable segment. |
| #UD 6 | c_ud0262 | If not in VMX operation. |
| #GP 13 | c_gp0263 | If the current privilege level is not 0. If the memory destination operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. |
| #SS 12 | c_ss0264 | If the memory destination operand is in the SS segment and the memory address is in a non-canonical form. |
| #GP 13 | c_gp0265 | If the current privilege level is not 0. |
| #GP 13 | c_gp0266 | If a memory source operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #GP 13 | c_gp0267 | If the DS, ES, FS, or GS register contains an unusable segment. |
| #GP 13 | c_gp0268 | If the source operand is located in an execute-only code segment. |
| #GP 13 | c_gp0269 | If the memory source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. |
| #PF 14 | c_pf0270 | If a page fault occurs in accessing a memory source operand. |
| #SS 12 | c_ss0271 | If a memory source operand effective address is outside the SS segment limit. |
| #SS 12 | c_ss0272 | If the SS register contains an unusable segment. |
| #SS 12 | c_ss0273 | If the memory source operand is in the SS segment and the memory address is in a non-canonical form. |
| #UD 6 | c_ud0274 | If executed outside VMX operation. |
| #GP 13 | c_gp0275 | If executed in VMX root operation with CPL > 0. |
| #SS 12 | c_ss0276 | If the memory source operand effective address is outside the SS segment limit. |
| #SS 12 | c_ss0277 | If the source operand is in the SS segment and the memory address is in a non-canonical form. |
| #GP 13 | c_gp0278 | If the memory source operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #GP 13 | c_gp0279 | If the source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. |
| #PF 14 | c_pf0280 | If a page fault occurs in accessing the memory source operand. |
| #SS 12 | c_ss0281 | If the memory destination operand effective address is outside the SS segment limit. |
| #SS 12 | c_ss0282 | If the destination operand is in the SS segment and the memory address is in a non-canonical form. |
| #GP 13 | c_gp0283 | If the memory destination operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #GP 13 | c_gp0284 | If the destination operand is located in a read-only data segment or any code segment. |
| #GP 13 | c_gp0285 | If the destination operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. |
| #PF 13 | c_pf0286 | If a page fault occurs in accessing the memory destination operand. |
| #GP 13 | c_gp0287 | If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #GP 13 | c_gp0288 | If the operand is located in an execute-only code segment. |
| #UD 6 | c_ud0289 | If executed with CR4.VMXE = 0. |
| #GP 13 | c_gp0290 | If executed outside VMX operation with CPL>0 or with invalid CR0 or CR4 fixed bits. |
| #GP 13 | c_gp0291 | If executed in A20M mode. |
| #UD 6 | c_ud0292 | If the logical processor does not support EPT (IA32_VMX_PROCBASED_CTLS2[33]=0). |
| #UD 6 | c_ud0293 | If the logical processor supports EPT (IA32_VMX_PROCBASED_CTLS2[33]=1) but does not support the INVEPT instruction (IA32_VMX_EPT_VPID_CAP[20]=0). |
| #SS 12 | c_ss0294 | If the memory operand effective address is outside the SS segment limit. |
| #SS 12 | c_ss0295 | If the memory operand is in the SS segment and the memory address is in a non-canonical form. |
| #GP 13 | c_gp0296 | If the memory operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. |
| #UD 6 | c_ud0297 | If the logical processor does not support VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=0). |
| #UD 6 | c_ud0298 | If the logical processor supports VPIDs (IA32_VMX_PROCBASED_CTLS2[37]=1) but does not support the INVVPID instruction (IA32_VMX_EPT_VPID_CAP[32]=0). |
| #UD 6 | c_ud0299 | If CPUID.01H:ECX.XSAVE[bit 26] = 0. |
| #UD 6 | c_ud0300 | If CR4.OSXSAVE[bit 18] = 0. |
| #GP 13 | c_gp0301 | If an invalid XCR is specified in ECX. |
| #GP 13 | c_gp0302 | If the value in EDX:EAX sets bits that are reserved in the XCR specified by ECX. |
| #GP 13 | c_gp0303 | If an attempt is made to clear bit 0 of XFEATURE_ENABLED_MASK. |
| #NM 7 | c_nm0304 | If CR0.TS[bit 3] = 1. |
| #SS 12 | c_ss0305 | If a memory operand effective address is outside the SS segment limit. |
| #SS 12 | c_ss0306 | If a memory address referencing the SS segment is in a noncanonical form. |
| #GP 13 | c_gp0307 | If a memory operand is not aligned on a 64-byte boundary, regardless of segment. |
| #GP 13 | c_gp0308 | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #GP 13 | c_gp0309 | If any part of the operand lies outside the effective address space from 0 to FFFFH. |
| #GP 13 | c_gp0310 | If the memory address is in a non-canonical form. |
| #PF 14 | c_pf0311 | If a page fault occurs. |
| #GP 13 | c_gp0312 | If a bit in XCR0 is 0 and the corresponding bit in HEADER.XSTATE_BV field of the source operand is 1. |
| #GP 13 | c_gp0313 | If bytes 23:8 of HEADER is not zero. |
| #GP 13 | c_gp0314 | If attempting to write any reserved bits of the MXCSR register with 1. |
| #UD 6 | c_ud0315 | Instruction not supported, as indicated by CPUID feature identifier. |
| #UD 6 | c_ud0316 | CR0.EM = 1. |
| #UD 6 | c_ud0317 | CR4.OSFXSR = 0. |
| #NM 7 | c_nm0318 | CR0.TS = 1. |
| #SS 12 | c_ss0319 | Memory address exceeding stack segment limit or non-canonical. |
| #GP 13 | c_gp0320 | Memory address exceeding data segment limit or non-canonical. |
| #GP 13 | c_gp0321 | Null data segment used to reference memory. |
| #PF 14 | c_pf0322 | Instruction execution caused a page fault. |
| #AC 17 | c_ac0323 | Unaligned memory reference with alignment checking enabled and MXCSR.MM = 1. |
| #GP 13 | c_gp0324 | Write to a read-only data segment. |
| #GP 13 | c_gp0325 | Memory operand not aligned on16-byte boundary while MXCSR.MM = 0. |
| #UD 6 | c_ud0326 | If CPUID.01H:ECX.MOVBE[bit 22] = 0 . |
| #GP 13 | c_gp0327 | If the destination operand is in a non-writable segment. |
| #GP 13 | c_gp0328 | If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #GP 13 | c_gp0329 | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD 6 | c_ud0330 | If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0. |
| #GP 13 | c_gp0331 | If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. |
| #UD 6 | c_ud0332 | Unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0, see SIMD Floating-Point Exceptions below for details. |
| #XF 19 | c_xf0333 | Undefined operation. |
| #XF 19 | c_xf0334 | A result could not be represented exactly in the destination format. |
| #XF 19 | c_xf0335 | Rounded result too large to fit into the format of the destination operand. |
| #XF 19 | c_xf0336 | Rounded result too small to fit into the format of the destination operand. |
| #UD 6 | c_ud0337 | CR4.OSXSAVE = 0, indicated by CPUID Fn0000_0001_ECX[OSXSAVE]. |
| #UD 6 | c_ud0338 | XfeatureEnabledMask[2:1] ! = 11b. |
| #GP 13 | c_gp0339 | VEX256: Memory operand not 32-byte aligned. VEX128: Memory operand not 16-byte aligned. |
| #XF 19 | c_xf0340 | Division of finite dividend by zero-value divisor. |
| #UD 6 | c_ud0341 | AVX instructions are only recognized in protected mode. |
| #AC 17 | c_ac0342 | 4 or 8-byte unaligned memory reference with alignment checking enabled and MXCSR.MM = 1. |
| #AC 17 | c_ac0343 | Unaligned memory reference with alignment checking enabled. |
| #UD 6 | c_ud0344 | XOP instructions are only recognized in protected mode. |
| #UD 6 | c_ud0345 | Unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions below for details. |
| #UD 6 | c_ud0346 | FMA4 instructions are only recognized in protected mode. |
| #UD 6 | c_ud0347 | VEX prefix |
| #UD 6 | c_ud0348 | If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. |
| #UD 6 | c_ud0349 | If XFEATURE_ENABLED_MASK[2:1] != 11b. |
| #UD 6 | c_ud0350 | If CR4.OSXSAVE[bit 18]=0. |
| #UD 6 | c_ud0351 | If any corresponding CPUID feature flag is 0 |
| #NM 7 | c_nm0352 | If CR0.TS[bit 3]=1 |
| #SS 12 | c_ss0353 | For an illegal address in the SS segment |
| #GP 13 | c_gp0354 | For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. |
| #PF 14 | c_pf0355 | For a page fault |
| #AC 17 | c_ac0356 | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD 6 | c_ud0357 | If CPUID.(EAX=0DH, ECX=01H):EAX.XSAVEOPT[bit 0] = 0. |
| #UD 6 | c_ud0358 | If CR4.FSGSBASE[bit 16] = 0. |
| #UD 6 | c_ud0359 | If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0. |
| #UD 6 | c_ud0360 | If CPUID.01H:ECX.RDRAND[bit 30] = 0. |
| #GP 13 | c_gp0361 | If the SRC contains a non-canonical address. |
| #UD 6 | c_ud0362 | If BMI1/BMI2 CPUID feature flag is 0 |
| #UD 6 | c_ud0363 | If a VEX prefix is present |
| #SS 12 | c_ss0364 | For an illegal address in the SS segment |
| #SS 12 | c_ss0365 | If a memory address referencing the SS segment is in a non-canonical form |
| #GP 13 | c_gp0366 | For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector. |
| #PF 14 | c_pf0367 | For a page fault |
| #AC 17 | c_ac0368 | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD 6 | c_ud0369 | BMI instructions are only recognized in protected mode. |
| #UD 6 | c_ud0370 | The BMI instructions are not supported, as indicated by EBX bit 3 of CPUID function 0000_0007h. |
| #UD 6 | c_ud0371 | The INVPCID instruction is not recognized in virtual-8086 mode. |
| #UD 6 | c_ud0372 | If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0. |
| #GP 13 | c_gp0373 | If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3. |
| #GP 13 | c_gp0374 | If bits 63:12 of INVPCID_DESC are not all zero. |
| #GP 13 | c_gp0375 | If CR4.PCIDE=0, INVPCID_DESC[11:0] is not zero, and INVPCID_TYPE is either 0, or 1. |
| #GP 13 | c_gp0376 | If INVPCID_TYPE is 0, INVPCID_DESC[127:64] is not a canonical address. |
| #GP 13 | c_gp0377 | If an invalid type is specified in the register operand. |
| #PF 14 | c_pf0378 | If a page fault occurs in accessing the memory operand. |
| #SS 12 | c_ss0379 | If a memory address referencing the SS segment is in a non-canonical form. |